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PRELIMINARY
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
s 50 MHz Operation s 6 Mbytes of Linear Address Space s 512 Bytes of Register RAM s 2 Kbytes of Code/Data RAM s Register-register Architecture s Footprint and Functionally Compatible Upgrade for the 8XC196NP and 80C196NU s Optional Phase-locked Loop (PLL) Circuitry with 2x or 4x Clock Multiplier s 32 I/O Port Pins s 19 Interrupt Sources, 14 with Programmable Priorities s 4 External Interrupt Pins and NMI Pin s 2 Flexible 16-bit Timer/Counters with Quadrature Counting Capability s 3 Pulse-width Modulator (PWM) Outputs with High Drive Capability s Full-duplex Serial Port with Dedicated Baud-rate Generator
s Chip-select Unit -- 6 Chip-select Pins -- Dynamic Demultiplexed/Multiplexed Address/Data Bus for Each Chip Select -- Programmable Wait States (0-15) for Each Chip Select -- Programmable Bus Width (8- or 16-bit) for Each Chip Select -- Programmable Address Range for Each Chip Select s Event Processor Array (EPA) with 4 High-speed Capture/Compare Channels s Multiply and Accumulate Executes in 80 ns Using the 40-bit Hardware Accumulator s 880 ns 32/16 Unsigned Division s 100-pin QFP Package s Complete System Development Support s High-speed CHMOS Technology
40 MHz standard; 50 MHz is Speed Premium
The 80296SA is a member of Intel's 16-bit MCS(R) 96 microcontroller family. The 80296SA features 6 Mbytes of linear address space, a demultiplexed bus, and a chip-select unit. The external bus can dynamically switch between multiplexed and demultiplexed operation. The device has hardware and instructions to support various digital signal processing algorithms. NOTE This datasheet contains information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
COPYRIGHT (c) INTEL CORPORATION, 1997
January 1997
Order Number: 272748-003
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. *Third-party brands and names are the property of their respective owners. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-548-4725
CONTENTS
80296SA Commercial CHMOS 16-bit Microcontroller 1.0 Product Overview ................................................................................................................ 1 2.0 Nomenclature Overview...................................................................................................... 2 3.0 Pinout .................................................................................................................................. 3 4.0 Signals ................................................................................................................................ 6 5.0 Address Map ..................................................................................................................... 13 6.0 Electrical Characteristics ................................................................................................... 14 6.1 DC Characteristics........................................................................................................ 14 6.2 AC Characteristics........................................................................................................ 18 6.2.1 Relationship of XTAL1 to CLKOUT ....................................................................... 18 6.2.2 Explanation of AC Symbols ................................................................................... 19 6.2.3 AC Characteristics -- Multiplexed Bus Mode ........................................................ 20 6.2.3.1 System Bus Timings, Multiplexed Bus ...................................................... 22 6.2.3.2 READY Timing, Multiplexed Bus ............................................................... 23 6.2.4 AC Characteristics -- Demultiplexed Bus Mode ................................................... 24 6.2.4.1 System Bus Timings, Demultiplexed Bus .................................................. 26 6.2.4.2 READY Timing, Demultiplexed Bus .......................................................... 27 6.2.4.3 80296SA Deferred Bus Timing Mode ........................................................ 28 6.2.5 HOLD#, HLDA# Timings ....................................................................................... 29 6.2.6 AC Characteristics -- Serial Port, Synchronous Mode 0 ...................................... 30 6.2.7 External Clock Drive .............................................................................................. 31 7.0 Thermal Characteristics .................................................................................................... 33 8.0 80296SA Errata................................................................................................................. 33 9.0 Datasheet Revision History ............................................................................................... 33 FIGURES 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 80296SA Block Diagram ......................................................................................................1 The 80296SA Family Nomenclature ....................................................................................2 80296SA 100-pin QFP Package ..........................................................................................3 ICC versus Frequency in Reset ........................................................................................... 17 Effect of Clock Mode on CLKOUT...................................................................................... 18 System Bus Timings, Multiplexed Bus Mode ..................................................................... 22 Example READY Timings at 50 MHz, Multiplexed Bus, BUSCONx = 1 Wait State........... 23 System Bus Timings, Demultiplexed Bus Mode................................................................. 26 Example READY Timings at 50 MHz, Demultiplexed Bus, BUSCONx = 1 Wait State ...... 27 Deferred Bus Mode Timing Diagram.................................................................................. 28 HOLD#, HLDA# Timing Diagram ....................................................................................... 29 Serial Port Waveform -- Synchronous Mode 0.................................................................. 30 External Clock Drive Waveforms........................................................................................ 31 AC Testing Input and Output Waveforms During 5.0 Volt Testing ..................................... 32 Float Waveforms During 5.0 Volt Testing........................................................................... 32
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CONTENTS
TABLES 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. Description of Product Nomenclature .................................................................................. 2 80296SA 100-pin QFP Pin Assignment ............................................................................... 4 80296SA 100-pin QFP Pin Assignment Arranged by Functional Categories ...................... 5 Signal Descriptions .............................................................................................................. 6 80296SA Address Map ...................................................................................................... 13 DC Characteristics Over Specified Operating Conditions.................................................. 14 AC Timing Symbol Definitions............................................................................................ 19 AC Characteristics the 80C296SA Will Meet, Multiplexed Bus Mode ................................ 20 AC Characteristics the External Memory System Must Meet, Multiplexed Bus Mode ....... 21 AC Characteristics the 80C296SA Will Meet, Demultiplexed Bus Mode ........................... 24 AC Characteristics the External Memory System Must Meet, Demultiplexed Bus Mode .. 25 HOLD#, HLDA# Timings .................................................................................................... 29 Serial Port Timing -- Synchronous Mode 0 ....................................................................... 30 External Clock Drive........................................................................................................... 31 Thermal Characteristics ..................................................................................................... 33
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80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
1.0
PRODUCT OVERVIEW
The 80296SA is a member of Intel's 16-bit MCS(R) 96 microcontroller family. The 80296SA features 6 Mbytes of linear address space, a demultiplexed bus, and a chip-select unit. The external bus can dynamically switch between multiplexed and demultiplexed operation. The device has hardware and instructions to support various digital signal processing algorithms.
Code/Data RAM (2 Kbytes)
Port 3
Memory Addr Bus (24) SIO Baudrate Generator
Memory Data Bus (16) Chip-select Unit Bus Controller Peripheral Bus Interface
Bus Control Signals A19:16 A15:0 AD15:0
Port 2
PWM Aligner Queue Port 4 Instruction Sequencer
Memory Data Bus (16) Memory Addr Bus (24)
Interrupt Controller EPA Timer 1 Timer 2
Source 1 Addr (24) Source 1 Data (16) Source 2 Addr (24) Source 2 Data (16) Memory Interface Unit
Peripheral Data Bus (16)
Peripheral Addr Bus (8)
Port 1
ALU
Register File (3-port RAM)
Destination Addr (24) Destination Data (16)
A3175-02
Figure 1. 80296SA Block Diagram
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80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
2.0
NOMENCLATURE OVERVIEW
X
Te
XX
Pa ck
8
X
Pr
X
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XX
ed pe eS vic De ily am tF uc od on Pr ati ns rm tio nfo Op sI ry es mo oc Pr me mra og
Figure 2. The 80296SA Family Nomenclature Table 1. Description of Product Nomenclature Parameter Temperature and Burn-in Options Packaging Options Program-memory Options Process Information Product Family Device Speed Options no mark S 0 no mark 296SA 40 50 Description Commercial operating temperature range (0C to 70C) with Intel standard burn-in. QFP Without ROM CHMOS -- 40 MHz 50 MHz
mp
ag i ng ti Op on s
atu er
a re nd
Bu -in rn
Op tio
ns
A2815-01
2
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80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
3.0
PINOUT
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
AD1 AD2 AD3 AD4 AD5 AD6 AD7 VCC AD8 VSS AD9 AD10 AD11 AD12 AD13 AD14 AD15 A16 / EPORT.0 A17 / EPORT.1 VCC
AD0 NC RESET# NMI NC A0 A1 VCC VSS A2 A3 A4 A5 A6 A7 VCC VSS PLLEN1 P3.0 / CS0# P3.1 / CS1# P3.2 / CS2# P3.3 / CS3# VSS P3.4 / CS4# P3.5 / CS5# P3.6 / EXTINT2 NC P3.7 / EXTINT3 P1.0 / EPA0 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
S80296SA
View of component as mounted on PC board
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VSS A18 / EPORT.2 A19 / EPORT.3 WR# / WRL# RD# BHE# / WRH# ALE INST READY RPD ONCE PLLEN2 VCC VSS A8 A9 A10 A11 A12 A13 A14 A15 VSS XTAL1 XTAL2 VSS P2.7 / CLKOUT VCC P2.6 / HLDA# P2.5 / HOLD#
P1.1 / EPA1 P1.2 / EPA2 P1.3 / EPA3 P1.4 / T1CLK P1.5 / T1DIR VCC P1.6 / T2CLK VSS P1.7 / T2DIR P4.0 / PWM0 P4.1 / PWM1 P4.2 / PWM2 P4.3 VCC VSS P2.0 / TXD P2.1 / RXD P2.2 / EXTINT0 P2.3 / BREQ# P2.4 / EXTINT1
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A3155-02
Figure 3. 80296SA 100-pin QFP Package
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80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 2. 80296SA 100-pin QFP Pin Assignment Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 AD0 NC (see Note) RESET# NMI NC (see Note) A0 A1 VCC VSS A2 A3 A4 A5 A6 A7 VCC VSS PLLEN1 CS0#/P3.0 CS1#/P3.1 CS2#/P3.2 CS3#/P3.3 VSS CS4#/P3.4 CS5#/P3.5 Name Pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Name EXTINT2/P3.6 NC (see Note) EXTINT3/P3.7 EPA0/P1.0 VCC EPA1/P1.1 EPA2/P1.2 EPA3/P1.3 T1CLK/P1.4 T1DIR/P1.5 VCC T2CLK/P1.6 VSS T2DIR/P1.7 PWM0/P4.0 PWM1/P4.1 PWM2/P4.2 P4.3 VCC VSS TXD/P2.0 RXD/P2.1 EXTINT0/P2.2 BREQ#/P2.3 EXTINT1/P2.4 Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Name HOLD#/P2.5 HLDA#/P2.6 VCC CLKOUT/P2.7 VSS XTAL2 XTAL1 VSS A15 A14 A13 A12 A11 A10 A9 A8 VSS VCC PLLEN2 ONCE RPD READY INST ALE BHE#/WRH# Pin 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 RD# WR#/WRL# EPORT.3/A19 EPORT.2/A18 VSS VCC EPORT.1/A17 EPORT.0/A16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 VSS AD8 VCC AD7 AD6 AD5 AD4 AD3 AD2 AD1 Name
NOTE:
For compatibility with future products, tie pin 5 to VCC and leave pins 2 and 27 unconnected.
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80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 3. 80296SA 100-pin QFP Pin Assignment Arranged by Functional Categories Address & Data Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 Pin 6 7 10 11 12 13 14 15 66 65 64 63 62 61 60 59 83 82 79 78 1 100 99 98 97 96 95 94 92 90 89 88 Processor Control Name CLKOUT EXTINT0 EXTINT1 EXTINT2 EXTINT3 NMI ONCE RESET# RPD XTAL1 XTAL2 PLLEN1 PLLEN2 Pin 54 48 50 26 28 4 70 3 71 57 56 18 69 ALE BHE#/WRH# BREQ# HOLD# HLDA# INST RD# READY WR#/WRL# Address & Data (continued) Name AD12 AD13 AD14 AD15 Pin 87 86 85 84 Input/Output Name CS0#/P3.0 CS1#/P3.1 CS2#/P3.2 CS3#/P3.3 CS4#/P3.4 CS5#/P3.5 EPA0/P1.0 EPA1/P1.1 EPA2/P1.2 EPA3/P1.3 EPORT.0 EPORT.1 EPORT.2 EPORT.3 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.6 P3.7 P4.3 PWM0/P4.0 PWM1/P4.1 PWM2/P4.2 RXD/P2.1 T1CLK/P1.4 T1DIR/P1.5 T2CLK/P1.6 T2DIR/P1.7 TXD/P2.0 Pin 19 20 21 22 24 25 29 31 32 33 83 82 79 78 48 49 50 51 52 54 26 28 43 40 41 42 47 34 35 37 39 46 NC NC NC No Connection Name Pin 2 5 27 VCC VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Power & Ground Name Pin 8 16 30 36 44 53 68 81 93 9 17 23 38 45 55 58 67 80 91
Bus Control & Status Name Pin 74 75 49 51 52 73 76 72 77
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80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
4.0
SIGNALS
Table 4. Signal Descriptions Name Type I/O System Address Bus These address pins provide address bits 0-15 during the entire external memory cycle during both multiplexed and demultiplexed bus modes. Description
A15:0
A19:16
I/O
Address Pins 16-19 These address pins provide address bits 16-19 during the entire external memory cycle during both multiplexed and demultiplexed bus modes, supporting extended addressing of the 1-Mbyte address space. NOTE: Internally, there are 24 address bits; however, only 20 external address pins (A19:0) are implemented. The internal address space is 16 Mbytes (000000-FFFFFFH) and the external address space is 1 Mbyte (00000- FFFFFH). The microcontroller resets to FF2080H. A19:16 share package pins with EPORT.3:0. Address/Data Lines These pins provide a multiplexed address and data bus. During the address phase of the bus cycle, address bits 0-15 are presented on the bus and can be latched using ALE or ADV#. During the data phase, 8- or 16-bit data is transferred. AD7:0 share package pins with P3.7:0. AD15:8 share package pins with P4.7:0.
AD15:0
I/O
ALE
O
Address Latch Enable This active-high output signal is asserted only during external memory cycles. ALE signals the start of an external bus cycle and indicates that valid address information is available on the system address/data bus (A19:16 and AD15:0 for a multiplexed bus; A19:0 for a demultiplexed bus). An external latch can use this signal to demultiplex address bits 0-15 from the address/data bus in multiplexed mode.
BHE#
O
Byte High Enable During 16-bit bus cycles, this active-low output signal is asserted for word and highbyte reads and writes to external memory. BHE# indicates that valid data is being transferred over the upper half of the system data bus. Use BHE#, in conjunction with address bit 0 (A0 for a demultiplexed address bus, AD0 for a multiplexed address/data bus), to determine which memory byte is being transferred over the system bus: BHE# 0 0 1
AD0 or A0 0 1 0
Byte(s) Accessed both bytes high byte only low byte only
BHE# shares a package pin with WRH#. Chip configuration register 0 (CCR0) determines whether this pin functions as BHE# or as WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects WRH#.
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80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 4. Signal Descriptions (Continued) Name BREQ# Type O Bus Request This active-low output signal is asserted during a hold cycle when the bus controller has a pending external memory cycle. When the bus-hold protocol is enabled (WSR.7 is set), the P2.3/BREQ# pin can function only as BREQ#, regardless of the configuration selected through the port configuration registers (P2_MODE, P2_DIR, and P2_REG). An attempt to change the pin configuration is ignored until the bushold protocol is disabled (WSR.7 is cleared). The microcontroller can assert BREQ# at the same time as or after it asserts HLDA#. Once it is asserted, BREQ# remains asserted until HOLD# is deasserted. BREQ# shares a package pin with P2.3. CLKOUT O Clock Output Output of the internal clock generator. The CLKOUT frequency is 1/2 the internal operating frequency (f). CLKOUT has a 50% duty cycle. CLKOUT shares a package pin with P2.7. CS5:0# O Chip-select Lines 0-5 The active-low output CSx# is asserted during an external memory cycle when the address to be accessed is in the range programmed for chip select x or chip select x+1 if remapping is enabled. If the external memory address is outside the range assigned to the six chip selects, no chip-select output is asserted and the bus configuration defaults to the CS5# values. Immediately following reset, CS0# is automatically assigned to the range FF2000- FF20FFH. CS5:0# share package pins with P3.5:0. EPA3:0 I/O Event Processor Array (EPA) Capture/Compare Channels High-speed input/output signals for the EPA capture/compare channels. For highspeed PWM applications, the outputs of two EPA channels (either EPA0 and EPA1 or EPA2 and EPA3) can be remapped to produce a PWM waveform on a shared output pin. EPA3:0 share package pins with P1.3:0. EPORT.3:0 I/O Extended Addressing Port This is a standard 4-bit, bidirectional port. EPORT.3:0 share package pins with A19:16. Description
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80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 4. Signal Descriptions (Continued) Name EXTINT3:0 Type I External Interrupts These programmable interrupts are controlled by the EXTINT_CON register. This register controls whether the interrupt is edge-triggered or level-sensitive and whether a rising edge/high level or falling edge/low level activates the interrupt. In standby and powerdown modes, asserting the EXTINTx signal causes the device to resume normal operation. The interrupt does not need to be enabled, but the pin must be configured as a special-function input. If the EXTINTx interrupt is enabled, the CPU executes the interrupt service routine. Otherwise, the CPU executes the instruction that immediately follows the command that invoked the power-saving mode. In idle mode, asserting any enabled interrupt causes the device to resume normal operation. EXTINT0 shares a package pin with P2.2, EXTINT1 shares a package pin with P2.4, EXTINT2 shares a package pin with P3.6, and EXTINT3 shares a package pin with P3.7. HLDA# O Bus Hold Acknowledge This active-low output indicates that the CPU has released the bus as the result of an external device asserting HOLD#. When the bus-hold protocol is enabled (WSR.7 is set), the P2.6/HLDA# pin can function only as HLDA#, regardless of the configuration selected through the port configuration registers (P2_MODE, P2_DIR, and P2_REG). An attempt to change the pin configuration is ignored until the bushold protocol is disabled (WSR.7 is cleared). HLDA# shares a package pin with P2.6. HOLD# I Bus Hold Request An external device uses this active-low input signal to request control of the bus. When the bus-hold protocol is enabled (WSR.7 is set), the P2.5/HOLD# pin can function only as HOLD#, regardless of the configuration selected through the port configuration registers (P2_MODE, P2_DIR, and P2_REG). An attempt to change the pin configuration is ignored until the bus-hold protocol is disabled (WSR.7 is cleared). HOLD# shares a package pin with P2.5. INST O Instruction Fetch When high, INST indicates that an instruction is being fetched from external memory. The signal remains high during the entire bus cycle of an external instruction fetch. INST is low for data accesses, including interrupt vector fetches and chip configuration byte reads. INST is low during internal memory fetches. Description
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80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 4. Signal Descriptions (Continued) Name NMI Type I Nonmaskable Interrupt In normal operating mode, a rising edge on NMI generates a nonmaskable interrupt. NMI has the highest priority of all interrupts except trap and unimplemented opcode. Assert NMI for greater than one state time to guarantee that it is recognized. If NMI is held high during and immediately following reset, the microcontroller will execute the NMI interrupt service routine when code execution begins. To prevent an inadvertent NMI interrupt vector, the first instruction (at F2080H) must clear the NMI pending interrupt bit. ANDB INT_PEND1, #7FH. During idle mode, a rising edge on NMI causes the microcontroller to exit idle mode and branch to the interrupt service routine. ONCE I On-circuit Emulation Holding ONCE high during the rising edge of RESET# places the microcontroller into on-circuit emulation (ONCE) mode. This mode puts all pins, except READY, RESET#, ONCE, and NMI, into a high-impedance state, thereby isolating the microcontroller from other components in the system. The value of ONCE is latched when the RESET# pin goes inactive. While the microcontroller is in ONCE mode, you can debug the system using a clip-on emulator. To exit ONCE mode, reset the microcontroller by pulling the RESET# signal low. To prevent inadvertent entry into ONCE mode, connect the ONCE pin to VSS. P1.7:0 I/O Port 1 This is a standard, 8-bit, bidirectional port that shares package pins with individually selectable special-function signals. Port 1 shares package pins with the following signals: P1.0/EPA0, P1.1/EPA1, P1.2/EPA2, P1.3/EPA3, P1.4/T1CLK, P1.5/T1DIR, P1.6/T2CLK, and P1.7/T2DIR. P2.7:0 I/O Port 2 This is a standard, 8-bit, bidirectional port that shares package pins with individually selectable special-function signals. Port 2 shares package pins with the following signals: P2.0/TXD, P2.1/RXD, P2.2/EXTINT0, P2.3/BREQ#, P2.4/EXTINT1, P2.5/HOLD#, P2.6/HLDA#, and P2.7/CLKOUT. P3.7:0 I/O Port 3 This is a standard, 8-bit, bidirectional port that shares package pins with individually selectable special-function signals. Port 3 shares package pins with the following signals: P3.0/CS0#, P3.1/CS1#, P3.2/CS2#, P3.3/CS3#, P3.4/CS4#, P3.5/CS5#, P3.6/EXTINT2, and P3.7/EXTINT3. P4.3:0 I/O Port 4 Port 4 is a standard, 4-bit, bidirectional I/O port with high-current drive capability. Port 4 shares package pins with the following signals: P4.0/PWM0, P4.1/PWM1, and P4.2/PWM2. P4.3 has a dedicated package pin. Description
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80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 4. Signal Descriptions (Continued) Name PLLEN2:1 Type I Phase-locked Loop 1 and 2 Enable These input pins enable the on-chip clock multiplier feature and select either the doubled or the quadrupled clock speed: PLLEN2 0 0 1 1
Description
PLLEN1 0 1 0 1
Mode 1x mode; PLL disabled; f = FXTAL1 2x mode; PLL enabled; f = 2FXTAL1 Reserved 4x mode; PLL enabled; f = 4FXTAL1
CAUTION: This reserved combination causes the device to enter an unsupported test mode. Pulse Width Modulator Outputs These are PWM output pins with high-current drive capability. The duty cycle and frequency-pulse-widths are programmable. PWM2:0 share package pins with P4.2:0.
PWM2:0
O
RD#
O
Read Read-signal output to external memory. RD# is asserted during external memory reads. Ready Input This active-high input can be used to insert wait states in addition to those programmed in chip configuration byte 0 (CCB0) and the bus control x register (BUSCONx). CCB0 is programmed with the minimum number of wait states (0, 5, 10, 15) for an external fetch of CCB1, and BUSCONx is programmed with the minimum number of wait states (0-15) for all external accesses to the address range assigned to the chip-select x channel. If the programmed number of wait states is greater than zero and READY is low when this programmed number of wait states is reached, additional wait states are added until READY is pulled high. If the programmed number of wait states is equal to zero, hold the READY pin high. Programming the number of wait states equal to zero and holding the READY pin low produces unpredictable results.
READY
I
RESET#
I/O
Reset A level-sensitive reset input to, and an open-drain system reset output from, the microcontroller. Either a falling edge on RESET# or an internal reset turns on a pulldown transistor connected to the RESET# pin for 16 state times. In the powerdown, standby, and idle modes, asserting RESET# causes the microcontroller to reset and return to normal operating mode. If the phase-locked loop (PLL) clock circuitry is enabled, you must hold RESET# low for at least 2 ms to allow the PLL to stabilize before the internal CPU and peripheral clocks are enabled. After a reset, the first instruction fetch is from FF2080H.
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Table 4. Signal Descriptions (Continued) Name RPD Type I Return from Powerdown Timing pin for the return-from-powerdown circuit. If your application uses powerdown mode, connect a capacitor between RPD and VSS if either of the following conditions are true. * the internal oscillator is the clock source * the phase-locked loop (PLL) circuitry is enabled (see PLLEN2:1 signal description) The capacitor causes a delay (at least 2 ms) that enables the oscillator and PLL circuitry to stabilize before the internal CPU and peripheral clocks are enabled. Refer to the "Special Operating Modes" chapter of the 80296SA Microcontroller User's Manual for details on selecting the capacitor. The capacitor is not required if your application uses powerdown mode and if both of the following conditions are true. * an external clock input is the clock source * the phase-locked loop circuitry is disabled If your application does not use powerdown mode, leave this pin unconnected. RXD I/O Receive Serial Data In modes 1, 2, and 3, RXD receives serial port input data. In mode 0, it functions as either an input or an open-drain output for data. RXD shares a package pin with P2.1. T1CLK I Timer 1 External Clock External clock for timer 1. Timer 1 increments (or decrements) on both rising and falling edges of T1CLK. Also used in conjunction with T1DIR for quadrature counting mode. and External clock for the serial I/O baud-rate generator input (program selectable). T1CLK shares a package pin with P1.4. T2CLK I Timer 2 External Clock External clock for timer 2. Timer 2 increments (or decrements) on both rising and falling edges of T2CLK. It is also used in conjunction with T2DIR for quadrature counting mode. T2CLK shares a package pin with P1.6. T1DIR I Timer 1 External Direction External direction (up/down) for timer 1. Timer 1 increments when T1DIR is high and decrements when it is low. Also used in conjunction with T1CLK for quadrature counting mode. T1DIR shares a package pin with P1.5. T2DIR I Timer 2 External Direction External direction (up/down) for timer 2. Timer 2 increments when T2DIR is high and decrements when it is low. It is also used in conjunction with T2CLK for quadrature counting mode. T2DIR shares a package pin with P1.7. Description
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80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 4. Signal Descriptions (Continued) Name TXD Type O Transmit Serial Data In serial I/O modes 1, 2, and 3, TXD transmits serial port output data. In mode 0, it is the serial clock output. TXD shares a package pin with P2.0. VCC VSS PWR GND Digital Supply Voltage Connect each VCC pin to the digital supply voltage. Digital Circuit Ground These pins supply ground for the digital circuitry. Connect each VSS pin to ground through the lowest possible impedance path. WR# O Write This active-low output indicates that an external write is occurring. This signal is asserted only during external memory writes. WR# shares a package pin with WRL#.
Description
Chip configuration register 0 (CCR0) determines whether this pin functions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.
WRH#
O
Write High During 16-bit bus cycles, this active-low output signal is asserted for high-byte writes and word writes to external memory. During 8-bit bus cycles, WRH# is asserted for all write operations. WRH# shares a package pin with BHE#.
Chip configuration registrer 0 (CCR0) determines whether this pin functions as BHE# or WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects WRH#.
WRL#
O
Write Low During 16-bit bus cycles, this active-low output signal is asserted for low-byte writes and word writes to external memory. During 8-bit bus cycles, WRL# is asserted for all write operations. WRL# shares a package pin with WR#.
Chip configuration register 0 (CCR0) determines whether this pin functions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.
XTAL1
I
Input Crystal/Resonator or External Clock Input Input to the on-chip oscillator, internal phase-locked loop circuitry, and the internal clock generators. The internal clock generators provide the peripheral clocks, CPU clock, and CLKOUT signal. When using an external clock source instead of the onchip oscillator, connect the clock input to XTAL1. The external clock signal must meet the VIH specification for XTAL1.
XTAL2
O
Inverted Output for the Crystal/Resonator Output of the on-chip oscillator inverter. Leave XTAL2 floating when the design uses an external clock source instead of the on-chip oscillator.
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5.0
ADDRESS MAP
Table 5. 80296SA Address Map Addressing Modes for Data Accesses Extended Extended Extended Extended -- -- Extended Indirect, indexed, extended, windowed direct Indirect, indexed, extended, windowed direct Indirect, indexed, extended Indirect, indexed, extended, windowed direct -- Indirect, indexed, extended -- Indirect, indexed, extended windowed direct Direct, indirect, indexed, extended Direct
Hex Address FFFFFF FFF800 FFF7FF FF2080 FF207F FF2000 FF1FFF FF0400 FF03FF FF0000 FEFFFF 0F0000 0EFFFF 010000 00FFFF 00F800 00F7FF 00F000 00EFFF 002000 001FFF 001F00 001EFF 001C00 001BFF 000400 0003FF 000200 0001FF 000100 0000FF 00001A 000019 000000
Description (Note 1, Note 2) External device (memory or I/O) in 1-Mbyte mode (CCB1.1=0) A copy of internal code RAM in 64-Kbyte mode (CCB1.1=1) External program memory (Note 3) External special-purpose memory (CCBs and interrupt vectors) External device (memory or I/O) connected to address/data bus Reserved for in-circuit emulators Overlaid memory (reserved for future devices); locations xF0000-xF03FFH are reserved for in-circuit emulators External device (memory or I/O) connected to address/data bus Internal code RAM (code or data); can be windowed by WSR1. In 64-Kbyte mode, code RAM is identically mapped into page FFH. External device (memory or I/O) connected to address/data bus; can be windowed by WSR1 External device (memory or I/O) connected to address/data bus Internal peripheral special-function registers (SFRs); can be windowed by WSR or WSR1 Reserved (future SFR expansion) External device (memory or I/O) connected to address/data bus Reserved (future register file expansion) Upper register file (general-purpose register RAM) can be windowed by WSR or WSR1 Lower register file (general-purpose register RAM) Lower register file (stack pointer and CPU SFRs)
NOTES: 1. Unless otherwise noted, write 0FFH to reserved memory locations and write 0 to reserved SFR bits. 2. The contents or functions of reserved locations may change in future device revisions, in which case a program that relies on one or more of these locations might not function properly. 3. External memory occupies the boot memory partition, FF2080-FF7FFH. After reset, the default chipselect line (CS0#) is active; the first instruction fetch is from FF2080H.
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6.0
ELECTRICAL CHARACTERISTICS
NOTICE: This datasheet contains information on new products in production. The specifications are Storage Temperature ................................... -60C to +150C subject to change without notice. Verify with your Supply Voltage with Respect to VSS............... -0.5 V to +7.0 V local Intel sales office that you have the latest Power Dissipation ........................................................... 1.5 W datasheet before finalizing a design. ABSOLUTE MAXIMUM RATINGS* OPERATING CONDITIONS*
TA (Ambient Temperature Under Bias) ................ 0C to +70C VCC (Digital Supply Voltage) ............................. 4.5 V to 5.5 V FXTAL1 (Input frequency for VCC = 4.5 V - 5.5 V) (Note 1, 2, 3)........................................ 16 MHz to 50 MHz
*WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
NOTES: 1. This device is static and should operate below 1 Hz, but has been tested only down to 16 MHz. 2. When the phase-locked loop (PLL) circuitry is enabled, the minimum input frequency on XTAL1 is 8 MHz. The PLL cannot be run at frequencies lower than 16 MHz. 3. Assumes an external clock. The maximum frequency for an external crystal oscillator is 25 MHz.
6.1
DC Characteristics
Table 6. DC Characteristics Over Specified Operating Conditions Typical (Note 1) 90 Test Conditions XTAL1 = 50 MHz VCC = 5.5 V Device in Reset XTAL1 = 50 MHz VCC = 5.5 V
Symbol ICC
Parameter VCC Supply Current
Min
Max 150
Units mA
IIDLE
Idle Mode Current
45
60
mA
NOTES: 1. Typical values are based on a limited number of samples and are not guaranteed. The values listed are at room temperature with VCC = 5.0 V. 2. For temperatures below 100C, typical is 10 A. 3. For all pins except P4.3:0, which have higher drive capability (see VOL1). 4. During normal (non-transient) conditions, the following maximum current limits apply for pin groups and individual pins: Group IOL (mA) IOH (mA) Individual IOL (mA) IOH (mA) P1.7:3, P4 40 40 P1, P2, P3 10 10 P2 40 40 P4 18 10 P1.2:0, P3 40 40 For all pins that were weakly pulled high during reset. This excludes ALE, INST, and NMI, which were weakly pulled low (see VOL2) and ONCE, which was pulled medium low (see VOL3). Pin capacitance is not tested. This value is based on design simulations.
5. 6.
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Table 6. DC Characteristics Over Specified Operating Conditions (Continued) Symbol IPD ISTDBY ILI VIL VIL1 VIH VIH1 VOL Parameter Powerdown Mode Current Standby Mode Input Leakage Current (Standard Inputs) Input Low Voltage (all pins) Input Low Voltage XTAL1 Input High Voltage Input High Voltage XTAL1 Output Low Voltage (output configured as complementary) (Note 3, 4) Output Low Voltage on P4.3:0 (output configured as complementary) (Note 4) Output Low Voltage in Reset on ALE, INST, and NMI Output Low Voltage in Reset on ONCE pin Output Low Voltage on XTAL2 -0.5 -0.5 0.2 VCC +1 0.7 VCC Min Typical (Note 1) 20 8 Max 50 15 10 0.8 0.3 VCC VCC + 0.5 VCC + 0.5 0.3 0.45 1.5 0.45 0.6 0.45 0.45 0.3 0.45 1.5 VCC - 0.5 VCC - 0.9 VCC - 1.5 VCC - 0.7 Units A mA A V V V V V V V V V V V V V V V V V V IOL = 200 A IOL = 3.2 mA IOL = 7.0 mA IOL = 8 mA IOL = 15 mA IOL = 3 A IOL = 30 A IOL = 100 A IOL = 700 A IOL = 3 mA IOH = -200 A IOH = -3.2 mA IOH = -7.0 mA IOH = -3 A Test Conditions VCC = 5.5 V (Note 2) VCC = 5.5 V VSS < VIN < VCC
VOL1
VOL2 VOL3 VOL4
VOH
Output High Voltage (output configured as complementary) (Note 4) Output High Voltage in Reset (Note 5)
VOH1
NOTES: 1. Typical values are based on a limited number of samples and are not guaranteed. The values listed are at room temperature with VCC = 5.0 V. 2. For temperatures below 100C, typical is 10 A. 3. For all pins except P4.3:0, which have higher drive capability (see VOL1). 4. During normal (non-transient) conditions, the following maximum current limits apply for pin groups and individual pins: Group P1.7:3, P4 P2 P1.2:0, P3 5. 6. IOL (mA) 40 40 40 IOH (mA) 40 40 40 Individual P1, P2, P3 P4 IOL (mA) 10 18 IOH (mA) 10 10
For all pins that were weakly pulled high during reset. This excludes ALE, INST, and NMI, which were weakly pulled low (see VOL2) and ONCE, which was pulled medium low (see VOL3). Pin capacitance is not tested. This value is based on design simulations.
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Table 6. DC Characteristics Over Specified Operating Conditions (Continued) Symbol VOH2 Parameter Output High Voltage on XTAL2 Min VCC - 0.3 VCC - 0.7 VCC - 1.5 VCC -1.1 0.3 10 50 150 Typical (Note 1) Max Units V V V V V pF k VCC = 5.5 V, VIN = 4.0 V Test Conditions IOH = -100 A IOH = -700 A IOH = -3 mA
VOH3 VTH+ - VTH- CS RRST
Output High Voltage on READY in Reset Hysteresis voltage width on RESET# pin Pin Capacitance (any pin to VSS) (Note 6) Reset Pull-up Resistor
NOTES: 1. Typical values are based on a limited number of samples and are not guaranteed. The values listed are at room temperature with VCC = 5.0 V. 2. For temperatures below 100C, typical is 10 A. 3. For all pins except P4.3:0, which have higher drive capability (see VOL1). 4. During normal (non-transient) conditions, the following maximum current limits apply for pin groups and individual pins: Group IOL (mA) IOH (mA) Individual IOL (mA) IOH (mA) P1.7:3, P4 P2 P1.2:0, P3 5. 6. 40 40 40 40 40 40 P1, P2, P3 P4 10 18 10 10
For all pins that were weakly pulled high during reset. This excludes ALE, INST, and NMI, which were weakly pulled low (see VOL2) and ONCE, which was pulled medium low (see VOL3). Pin capacitance is not tested. This value is based on design simulations.
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140
120
100
ICC (mA)
80
60
40
20
0 0 5 10 15 20 25 30 35 40 45 50
Frequency (MHz)
A4379-01
Figure 4. ICC versus Frequency in Reset
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6.2
6.2.1
AC Characteristics
RELATIONSHIP OF XTAL1 TO CLKOUT
TXHCH XTAL1 (12.5 MHz)
f PLLEN2:1=00
t = 80ns
CLKOUT
f PLLEN2:1=01
t = 40ns
CLKOUT
f PLLEN2:1=11 t = 20ns
CLKOUT
A3160-02
Figure 5. Effect of Clock Mode on CLKOUT
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6.2.2
EXPLANATION OF AC SYMBOLS
Each AC timing symbol is two pairs of letters prefixed by "T" for time. The characters in a pair indicate a signal and its condition, respectively. Symbols represent the time between the two signal/condition points. Table 7. AC Timing Symbol Definitions Character A B BR C D H HA L Q R S W X Y Character H L V X Z High Low Valid No Longer Valid Floating (low impedance) AD15:0, A19:0 BHE# BREQ# CLKOUT AD15:0, AD7:0, RXD (SIO mode 0 input data) HOLD# HLDA# ALE AD15:0, AD7:0, RXD (SIO mode 0 output data) RD# CSx# WR#, WRH#,WRL# XTAL1, TXD (SIO clock) READY Condition Signal(s)
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6.2.3 AC CHARACTERISTICS -- MULTIPLEXED BUS MODE
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns. Table 8. AC Characteristics the 80C296SA Will Meet, Multiplexed Bus Mode Symbol FXTAL1 Parameter Frequency on XTAL1, PLL in 1x mode Frequency on XTAL1, PLL in 2x mode Frequency on XTAL1, PLL in 4x mode f Operating frequency, f = FXTAL1; PLL in 1x mode Operating frequency, f = 2FXTAL1; PLL in 2x mode Operating frequency, f = 4FXTAL1; PLL in 4x mode t TXHCH TCLCL TCHCL TAVWL TCLLH TLLCH TLHLH TLHLL TAVLL TLLAX TLLRL TRLCL TRLRH TRHLH TRLAZ TLLWL TQVWH TCHWH TWLWH Period, t = 1/f XTAL1 Rising Edge to CLKOUT High or Low CLKOUT Cycle Time CLKOUT High Period Address Valid to WR# Falling Edge CLKOUT Falling Edge to ALE Rising Edge ALE Falling Edge to CLKOUT Rising Edge ALE Cycle Time ALE High Period Address Valid to ALE Falling Edge Address Hold after ALE Falling Edge ALE Falling Edge to RD# Falling Edge RD# Low to CLKOUT Falling Edge RD# Low Period RD# Rising Edge to ALE Rising Edge RD# Low to Address Float ALE Falling Edge to WR# Falling Edge Data Stable to WR# Rising Edge CLKOUT High to WR# Rising Edge WR# Low Period 4 2t - 27 -15 2t - 25 5 t - 10 2t - 25 -13 -15 4t t - 10 t - 15 1 3 -10 2t - 25 t-5 t + 15 5 20 t + 10 10 15 20 3 2t t + 15 62.5 50 ns ns ns ns ns ns ns ns (3) ns ns ns ns ns ns (3) ns (4) ns ns 16 50 MHz Min 16 8 (2) 8 (2) Max 50 (1) 25 12.5 Units MHz MHz MHz
ns (3)
ns ns (3)
NOTES: 1. 25 MHz is the maximum input frequency when using an external crystal oscillator; however, 50 MHz can be applied with an external clock source. 2. When the phase-locked loop (PLL) circuitry is enabled, the minimum input frequency on XTAL1 is 8 MHz. The PLL cannot be run at frequencies lower than 16 MHz. 3. If wait states are used, add 2t x n, where n = number of wait states. 4. Assuming back-to-back bus cycles. 5. 8-bit bus only.
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Table 8. AC Characteristics the 80C296SA Will Meet, Multiplexed Bus Mode (Continued) Symbol TWHQX TWHLH TWHBX TWHAX TRHBX TRHAX TWHSH TRHSH Parameter Data Hold after WR# Rising Edge WR# Rising Edge to ALE Rising Edge BHE#, INST Hold after WR# Rising Edge AD15:8 Hold after WR# Rising Edge BHE#, INST Hold after RD# Rising Edge AD15:8 Hold after RD# Rising Edge A19:16, CS# Hold after WR# Rising Edge A19:16, CS# Hold after RD# Rising Edge Min t-7 t - 15 0 t-4 0 t-4 0 0 t + 20 Max Units ns ns ns ns (5) ns ns (5) ns ns
NOTES: 1. 25 MHz is the maximum input frequency when using an external crystal oscillator; however, 50 MHz can be applied with an external clock source. 2. When the phase-locked loop (PLL) circuitry is enabled, the minimum input frequency on XTAL1 is 8 MHz. The PLL cannot be run at frequencies lower than 16 MHz. 3. If wait states are used, add 2t x n, where n = number of wait states. 4. Assuming back-to-back bus cycles. 5. 8-bit bus only.
Table 9. AC Characteristics the External Memory System Must Meet, Multiplexed Bus Mode Symbol TAVDV TRLDV TSLDV TCHDV TRHDZ TRXDX TAVYV TCH1YX TCH2YX TYLYH Parameter AD15:0 Valid to Input Data Valid RD# Active to Input Data Valid Chip Select Low to Data Valid CLKOUT High to Input Data Valid End of RD# to Input Data Float Data Hold after RD# Inactive AD15:0 Valid to READY (Inactive) Setup First READY Hold (active) after CLKOUT High Non-first READY Hold (active) after CLKOUT High Non-READY (Inactive) Time t-4 0 2t 0 2t - 42 2t - 21 2t - 21 No Upper Limit Min Max 3t - 32 2t - 40 4t - 28 2t - 25 t-3 Units ns (1, 2) ns (1, 2) ns (1, 2) ns ns (2) ns ns (3) ns (4, 5) ns (4) ns
NOTES: 1. If using the READY signal to insert wait states, you must program at least one wait state in the BUSCONx register because the first falling edge of READY is not synchronized with a CLKOUT edge. 2. If using the BUSCONx register without the READY signal to insert wait states, add 2t x n, where n = number of wait states. 3. If using the BUSCONx register to insert wait states, add 2t x (n-1), where n = number of wait states. 4. Exceeding the maximum specification causes additional wait states. 5. If you program two or more wait states in the BUSCONx register, the TCH1YX minimum does not apply.
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6.2.3.1 System Bus Timings, Multiplexed Bus
TCLCL t TCLLH TCHDV TRLCL TCHCL
CLKOUT
TLLCH TLHLH TLLRL TRHLH TLHLL
ALE
TRLRH TRLAZ TRHDZ
RD#
TAVLL TRLDV TLLAX TAVDV Data In TLLWL TWLWH TCHWH TWHLH TWHQX
AD15:0 (read)
Address Out
WR#
TQVWH
AD15:0 (write) BHE#, INST
Address Out
Data Out
Address Out TWHBX, TRHBX
TWHAX, TRHAX
AD15:8 (8-bit mode) A19:16 CSx#
High Address Out
Extended Address Out TWHSH, TRHSH
A3251-01
Figure 6. System Bus Timings, Multiplexed Bus Mode
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6.2.3.2
READY Timing, Multiplexed Bus
CH0
CH1 TCH1YX t t TYLYH t t
CH2 t t
CH3
CLKOUT First READY Non-first READY ALE
TAVYV
TCH2YX
TLHLH + 2t
TRLRH + 2t
RD# AD15:0 (read) WR# AD15:0 (write) BHE#,INST A19:16 CS0#
A5330-01
TRLDV + 2t TAVDV + 2t Addr Out TWLWH + 2t TQVWH + 2t Addr Out Data Out Data In
Figure 7. Example READY Timings at 50 MHz, Multiplexed Bus, BUSCONx = 1 Wait State
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6.2.4 AC CHARACTERISTICS -- DEMULTIPLEXED BUS MODE
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns. Table 10. AC Characteristics the 80C296SA Will Meet, Demultiplexed Bus Mode Symbol FXTAL1 Parameter Frequency on XTAL1, PLL in 1x mode Frequency on XTAL1, PLL in 2x mode Frequency on XTAL1, PLL in 4x mode f Operating frequency, f = FXTAL1; PLL in 1x mode Operating frequency, f = 2FXTAL1; PLL in 2x mode Operating frequency, f = 4FXTAL1; PLL in 4x mode t TAVWL TAVRL TRHRL TXHCH TCLCL TCHCL TCLLH TLLCH TLHLH TLHLL TRLCL TRLRH TRHLH TWLCL TQVWH TCHWH TWLWH TWHQX TWHLH Period, t = 1/f Address Valid to WR# Falling Edge Address Valid to RD# Falling Edge Read High to Next Read Low XTAL1 High to CLKOUT High or Low CLKOUT Cycle Time CLKOUT High Period CLKOUT Falling Edge to ALE Rising Edge ALE Falling Edge to CLKOUT Rising Edge ALE Cycle Time ALE High Period RD# Low to CLKOUT Falling Edge RD# Low Period RD# Rising Edge to ALE Rising Edge WR# Low to CLKOUT Falling Edge Data Stable to WR# Rising Edge CLKOUT High to WR# Rising Edge WR# Low Period Data Hold after WR# Rising Edge WR# Rising Edge to ALE Rising Edge t - 10 -13 -15 4t t - 10 -5 3t - 18 t-4 -8 3t - 10 -11 3t - 10 t-5 t-5 t + 20 t + 10 10 t + 15 9 t + 10 11 20 t - 10 t - 10 t-5 3 2t t + 15 10 15 50 62.5 ns ns ns ns ns ns ns ns ns ns (3,4) ns ns ns (3) 16 50 MHz Min 16 8 (2) 8 (2) Max 50 (1) 25 12.5 Units MHz MHz MHz
ns (4)
ns ns (4) ns ns (3) ns ns (3)
NOTES: 1. 25 MHz is the maximum input frequency when using an external crystal oscillator; however, 50 MHz can be applied with an external clock source. 2. When the phase-locked loop (PLL) circuitry is enabled, the minimum input frequency on XTAL1 is 8 MHz. The PLL cannot be run at frequencies lower than 16 MHz. 3. If using either READY or BUSCONx to insert wait states, add 2t x n, where n = number of wait states. 4. Assuming back-to-back bus cycles.
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Table 10. AC Characteristics the 80C296SA Will Meet, Demultiplexed Bus Mode (Continued) Symbol TWHBX TWHAX TRHBX TRHAX Parameter BHE#, INST Hold after WR# Rising Edge A19:0, CSx# Hold after WR# Rising Edge BHE#, INST Hold after RD# Rising Edge A19:0, CSx# Hold after RD# Rising Edge Min 0 0 0 0 Max Units ns ns ns ns
NOTES: 1. 25 MHz is the maximum input frequency when using an external crystal oscillator; however, 50 MHz can be applied with an external clock source. 2. When the phase-locked loop (PLL) circuitry is enabled, the minimum input frequency on XTAL1 is 8 MHz. The PLL cannot be run at frequencies lower than 16 MHz. 3. If using either READY or BUSCONx to insert wait states, add 2t x n, where n = number of wait states. 4. Assuming back-to-back bus cycles.
Table 11. AC Characteristics the External Memory System Must Meet, Demultiplexed Bus Mode Symbol TAVDV TRLDV TSLDV TCHDV TRHDZ TRXDX TAVYV TCH1YX TCH2YX TYLYH Parameter A19:0 Valid to Input Data Valid RD# Active to Input Data Valid Chip Select Low to Data Valid CLKOUT High to Input Data Valid End of RD# to Input Data Float Data Hold after RD# Inactive A19:0 Valid to READY Setup First READY Hold (active) after CLKOUT High Non-first READY Hold (active) after CLKOUT High Non READY (inactive) Time t-4 0 2t 0 3t - 45 2t - 21 2t - 21 No Upper Limit Min Max 4t - 28 3t - 25 4t - 28 2t - 25 t Units ns (1, 2, 3) ns (1, 2) ns (1, 2, 3) ns ns (2, 3) ns ns (4) ns (5, 6) ns (5) ns
NOTES: 1. If using the READY signal to insert wait states, you must program at least one wait state in the BUSCONx register because the first falling edge of READY is not synchronized with a CLKOUT edge. 2. If using the BUSCONx register without the READY signal to insert wait states, add 2t x n, where n = number of wait states. 3. If CSx# changes or if a write cycle follows a read cycle, add 2t (1 state). 4. If using the BUSCONx register to insert wait states, add (2t x n-1), where n = number of wait states. 5. Exceeding the maximum specification causes additional wait states. 6. If you program two or more wait states in the BUSCONx register, the TCH1YX minimum does not apply.
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6.2.4.1 System Bus Timings, Demultiplexed Bus
TCHCL TCLLH
TCLCL
t TCHWH
CLKOUT
TLHLH TLLCH TWHLH TRHLH TLHLL
ALE
TRHRL TRHDZ TRHAX
TAVRL
TRLRH TCHDV TRLDV TAVDV TSLDV Data In TWLCL
RD#
AD15:0 (read)
TAVWL
TWHQX TWHAX TWLWH
WR#
TQVWH
AD15:0 (write) BHE#, INST A19:0 CSx#
Address Out
Data Out TWHBX, TRHBX
A3253-02
Figure 8. System Bus Timings, Demultiplexed Bus Mode
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6.2.4.2
READY Timing, Demultiplexed Bus
CH0
CH1 t TYLYH t t TCH1YX
CH2 t t
CH3
CLKOUT First READY
t TAVYV
TAVYV
TCH2YX TLHLH + 2t
Non-first READY ALE
TRLRH + 2t
RD#
TRLDV + 2t
AD15:0 (read) WR#
TAVDV + 2t Data In TWLWH + 2t
TQVWH + 2t
AD15:0 (write) BHE#,INST A19:0 CSx#
Address Out
Data Out
A3258-02
Figure 9. Example READY Timings at 50 MHz, Demultiplexed Bus, BUSCONx = 1 Wait State
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6.2.4.3 80296SA Deferred Bus Timing Mode
The deferred bus cycle mode is designed to reduce bus contention when using the 80296SA in demultiplexed mode with slow memory devices. Unlike the 8XC196NU, in which this bus mode has to be enabled through the CCR to take advantage of the feature, the 80296SA automatically invokes this mode whenever the appropriate conditions occur. In the deferred mode, a delay of the WR# signal and the next bus cycle will occur in the first bus cycle following a chip-select change and in the first write cycle following a read cycle. This mode will work in parallel with wait states. Refer to Figure 11 to determine which control signals are affected. Cycle 1 is a normal 4t read cycle. Cycle 2 is a write cycle that follows a read cycle, so a 2t delay of the next bus cycle is inserted. Notice that the chip-select change at the beginning of cycle 2 did not cause a double delay (4t). The chip-select change in cycle 3, a read cycle, causes a 2t delay.
CLKOUT
TLHLH + 2t TWHLH + 2t
ALE
TRHLH + 2t TAVRL + 2t
RD#
TAVDV + 2t
AD15:0 (read) WR# AD15:0 (write) BHE#, INST A19:0 CSx#
Data In TAVWL + 2t
Data In
Data Out
Data Out
Data Out
Address Out
Valid
Valid
A3247-02
Figure 10. Deferred Bus Mode Timing Diagram
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6.2.5
HOLD#, HLDA# TIMINGS Table 12. HOLD#, HLDA# Timings
Symbol THVCH TCLHAL TCLBRL THALAZ THALBZ TCLHAH TCLBRH THAHAX THAHBV
Parameter HOLD# Setup time (to guarantee recognition at next clock) CLKOUT Low to HLDA# Low CLKOUT Low to BREQ# Low HLDA# Low to Address Float HLDA# Low to BHE#, INST, RD#, WR# Weakly Driven CLKOUT Low to HLDA# High CLKOUT Low to BREQ# High HLDA# High to Address No Longer Float HLDA# High to BHE#, INST, RD#, WR# Valid
Min 30 -15 -15
Max
Units ns
15 15 33 25
ns ns ns ns ns ns ns ns
-25 -25 -20 -20
15 25
CLKOUT
THVCH
HOLD#
THVCH
Hold Latency
TCLHAL
HLDA#
TCLHAH
TCLBRL
BREQ#
TCLBRH
THALAZ
A19:0, AD15:0 CSx#, BHE#, INST, RD#, WR# WRL#, WRH# ALE
THAHAX THAHBV
Weakly held inactive
THALBZ
TCLLH
Start of strongly driven ALE
A2460-03
Figure 11. HOLD#, HLDA# Timing Diagram
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6.2.6 AC CHARACTERISTICS -- SERIAL PORT, SYNCHRONOUS MODE 0 Table 13. Serial Port Timing -- Synchronous Mode 0 Symbol TXLXL Parameter Serial Port Clock period SP_BAUD x002H SP_BAUD = x001H
Min 6t 4t 4t - 15 2t - 15 4t - 15 2t - 15 2t - 20
Max
Units ns ns
TXLXH
Serial Port Clock falling edge to rising edge SP_BAUD x002H SP_BAUD = x001H Output data setup to clock high (see Note) SP_BAUD x002H SP_BAUD = x001H Output data hold after clock high Next output data valid after clock high Input data setup to clock high (see Note) SP_BAUD x002H SP_BAUD = x001H Input data hold after clock high Last clock high to output float
4t + 15 2t + 15 4t + 15 2t + 15
ns ns ns ns
TQVXH
TXHQX TXHQV TDVXH
2t + 20 2t + 10 t + 10 0 2t + 15
ns ns ns ns
TXHDX TXHQZ
The minimum baud-rate (SP_BAUD) register value is x002H for receptions and x001H for transmissions.
TXLXL TXD TQVXH RXD (Out) 0 TDVXH RXD (In) Valid Valid Valid 1 2 3 TXHDX Valid Valid Valid Valid Valid 4
TXLXH
TXHQV TXHQX 5 6 TXHQZ 7
A2080-02
Figure 12. Serial Port Waveform -- Synchronous Mode 0
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6.2.7
EXTERNAL CLOCK DRIVE Table 14. External Clock Drive Parameter External Input Frequency (1/TXLXL), PLL disabled External Input Frequency (1/TXLXL), PLL in 2x mode External Input Frequency (1/TXLXL), PLL in 4x mode Min 16 8 8 20 40 80 0.35TXTAL1 0.35TXTAL1 Max 50
Symbol FXTAL1
Units MHz MHz MHz ns ns ns ns ns ns ns
25 12.5 62.5 125 125 0.65TXTAL1 0.65TXTAL1 10 10
TXTAL1
Oscillator Period (TXLXL), PLL disabled Oscillator Period (TXLXL), PLL in 2x mode Oscillator Period (TXLXL), PLL in 4x mode
TXHXX TXLXX TXLXH TXHXL
High Time Low Time Rise Time Fall Time
Assumes an external clock; the maximum input frequency for an external crystal oscillator is 25 MHz.
TXHXX 0.7 VCC + 0.5 V
XTAL1
TXLXH TXLXX 0.3 VCC - 0.5 V 0.7 VCC + 0.5 V 0.3 VCC - 0.5 V TXLXL
TXHXL
A2119-03
Figure 13. External Clock Drive Waveforms
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3.5 V
2.0 V Test Points 0.8 V
2.0 V 0.8 V
0.45 V
Note: AC testing inputs are driven at 3.5 V for a logic "1" and 0.45 V for a logic "0". Timing measurements are made at 2.0 V for a logic "1" and 0.8 V for a logic "0".
A2120-04
Figure 14. AC Testing Input and Output Waveforms During 5.0 Volt Testing
VLOAD + 0.15 V VLOAD VLOAD - 0.15 V Timing Reference Points
VOH - 0.15 V
VOL + 0.15 V
Note: For timing purposes, a port pin is no longer floating when a 150 mV change from load voltage occurs and begins to float when a 150 mV change from the loading VOH/VOL level occurs with IOL/IOH 15 mA.
A2121-03
Figure 15. Float Waveforms During 5.0 Volt Testing
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7.0
THERMAL CHARACTERISTICS
All thermal impedance data is approximate for static air conditions at 1 watt of power dissipation. Values will change depending on operating conditions and the application. The Intel Packaging Handbook (order number 240800) describes Intel's thermal impedance test methodology. The Components Quality and Reliability Handbook (order number 210997) provides quality and reliability information. Table 15. Thermal Characteristics Package Type 100-pin QFP JA 50C/W JC 16C/W
8.0
80296SA ERRATA
The 80296SA may contain design defects or errors known as errata. Characterized errata that may cause the 80296SA's behavior to deviate from published specifications are documented in a specification update. Specification updates can be obtained from your local Intel sales office or from the World Wide Web (www.intel.com).
9.0
DATASHEET REVISION HISTORY
This datasheet is valid for devices with an "A" at the end of the topside tracking number. Datasheets are changed as new device information becomes available. Verify with your local Intel sales office that you have the latest version before finalizing a design or ordering devices. This is the -003 version of the datasheet. The following changes were made in this version: 1. 2. 3. 4. 5. 6. All references to SQFP package were deleted. Reference to ROM option was removed from Table 1. The speed designation for 40 MHz was changed from "no mark" to "40" in Table 1. The TRXDX specification was changed to 0 ns (from 2 ns) in Table 11 and Table 13. The TCHYX specification was replaced by TCH1YX and TCH2YX. The READY timing diagrams (Figures 8 and 10) were replaced by examples that reflect the new TCH1YX and TCH2YX specifications.
This is the -002 version of the datasheet. The following changes were made in this version: 1. 2. 3. The "Intel Confidential" designation was removed for publication. A heading was added for Section 1.0, "Product Overview," and the remaining sections were renumbered. The errata list was replaced with a reference to the specification update document.
The following changes were made in the -001 version of the datasheet: 1. 2. 3. 4. 5. Throughout the datasheet, the product name was changed to read "80296SA" instead of "80C296SA." The feature list was clarified. A table of contents was added. The block diagram was changed. Several sections were rearranged and section numbers were assigned. "Thermal Characteristics" was moved to Section 7.0; a section heading was added for "Nomenclature Overview," Section 2.0; a section heading was added for "Address Map" and it was moved to Section 5.0; a section heading was added for "Pinout," and it was moved to Section 3.0; the section heading "Pin Descriptions" was changed to "Signals," Section 4.0. The remaining sections were assigned section numbers: "Electrical Characteris-
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tics" is Section 6.0; "Errata" is Section 8.0, and "Datasheet Revision History" is Section 9.0. Table 2 was changed to Table 1 and the "process information" was corrected to show that "no mark" signifies a CHMOS process. Table 3 was changed to Table 7 and several clarifications were made. Figure 3 was changed to correct the product name. Pin assignments did not change. Table 4 was changed to Table 2 and pin 3 was changed from "no connection" to "tie to VCC." Figure 4 was changed to correct the product name. Pin assignments did not change. Figure 5, "ICC versus Frequency in Reset," was added. Remaining figure numbers were incremented. Table 6 was changed to Table 4 and a note for handling the "no connection" pins was added. Table 8 was changed to Table 6. The descriptions of BREQ#, HLDA#, and HOLD# were changed to reflect their operation during hold. The description of the ONCE signal was changed to reflect the correct states of READY, RESET#, and NMI during ONCE mode. The description of PLLEN2:1 was changed to show the correct pin states to achieve each phase-locked loop (PLL) clock multiplier mode. The descriptions of RPD and RESET# were changed to reflect system requirements when using the PLL. Two notes were added to clarify the "Operating Conditions" in the "Electrical Characteristics" section. Table 9 was changed to Table 8, the notes were re-ordered, and the following specifications were changed: * ICC max was changed to 150 mA (from 120 mA). * VOH min was changed to VCC-0.5 V (from VCC-0.3 V) at IOH = -200A. * VOH min was changed to VCC-0.9 V (from VCC-0.7V) at IOH = -3.2 mA. * Test condition for VOL1 max = 0.45 V was changed to IOL = 8 mA (from IOL = 10 mA). * RRST min and max were changed to 50 k and 150 k (from 9 k and 95 k). * VOH3 min specification was added. Table 10 was divided into two tables: timing specifications that the microcontroller will meet (Table 10) and those that the external memory system must meet (Table 11). Note 7 was deleted and the remaining notes were re-ordered. The following specifications were changed or added in Table 10: * FXTAL1 min for the PLL in 4x mode was changed to 8 MHz (from 4 MHz); a clarifying note was added. * TXHCH min was changed to 3 ns (from TBD). * TLLAX min was changed to 1 ns (from TBD). * TLLRL min was changed to 3 ns (from TBD) * TRHAX min was changed to t - 4 ns (from t). * TAVWL min (2t - 25) was added to Table 10. * TSLDV min (4t - 28) was added to Table 11. Table 11 was divided into two tables: timing specifications that the microcontroller will meet (Table 12) and those that the external memory system must meet (Table 13). Note 7 was deleted and the remaining notes were re-ordered. The following specifications were changed: * FXTAL1 min for the PLL in 4x mode was changed to 8 MHz (from 4 MHz); a clarifying note was added. * TWHQX min was changed to t - 5 ns (from t - 2 ns). Figure 6 was changed to show the correct PLLEN2:1 values to select the 2x clock multiplier mode. Table 13 was changed to Table 15 and a note was added. Table 14 was changed to Table 16, 1/TXLXL specifications for each phase-locked loop (PLL) mode were added, and Note 2 was deleted.
6. 7. 8. 9. 10. 11. 12. 13.
14. 15.
16.
17.
18. 19. 20.
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